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| R8C/16 Group, R8C/17 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ03B0101-0200 Rev.2.00 Jan 30, 2006 1. Overview This MCU is built using the high-performance silicon gate CMOS process using the R8C/Tiny Series CPU core and is packaged in a 20-pin plastic molded LSSOP. This MCU operates using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, it is capable of executing instructions at high speed. Furthermore, the data flash ROM (1KB x 2blocks) is embedded in the R8C/17 group. The difference between the R8C/16 and R8C/17 groups is only the existence of the data flash ROM. Their peripheral functions are the same. 1.1 Applications Electric household appliance, office equipment, housing equipment (sensor, security), general industrial equipment, audio, etc. Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 1 of 35 R8C/16 Group, R8C/17 Group 1. Overview 1.2 Performance Overview Table 1.1 lists the Performance Outline of the R8C/16 Group and Table 1.2 lists the Performance Outline of the R8C/17 Group. Table 1.1 Performance Outline of the R8C/16 Group Item Performance CPU Number of Basic Instructions 89 instructions Minimum Instruction 50ns(f(XIN)=20MHz, VCC=3.0 to 5.5V) Execution Time 100ns(f(XIN)=10MHz, VCC=2.7 to 5.5V) Operating Mode Single-chip Address Space 1 Mbyte Memory Capacity See Table 1.3 R8C/16 Group Product Information Peripheral Port I/O port : 13 pins (including LED drive port), Function Input : 2 pins LED Drive Port I/O port: 4 pins Timer Timer X: 8 bits x 1 channel, Timer Z: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer C: 16 bits x 1 channel (Circuits of input capture and output compare) Serial Interface 1 channel Clock synchronous serial I/O, UART 1 channel I2C bus Interface (IIC)(1) A/D Converter 10-bit A/D converter: 1 circuit, 4 channels Watchdog Timer 15 bits x 1 channel (with prescaler) Reset start selectable, Count source protection mode Interrupt Internal: 9 factors, External: 4 factors, Software: 4 factors Priority level: 7 levels Clock Generation Circuit 2 circuits Main clock oscillation circuit (Equipped with a built-in feedback resistor) On-chip oscillator (high speed, low speed) Equipped with frequency adjustment function on highspeed on-chip oscillator Oscillation Stop Detection Main clock oscillation stop detection function Function Voltage Detection Circuit Included Power-on Reset Circuit Included Electric Supply Voltage VCC=3.0 to 5.5V (f(XIN)=20MHz) Characteristics VCC=2.7 to 5.5V (f(XIN)=10MHz) Power Consumption Typ. 9mA (VCC=5.0V, f(XIN)=20MHz) Typ. 5mA (VCC=3.0V, f(XIN)=10MHz) Typ. 35A (VCC=3.0V, wait mode, peripheral clock off) Typ. 0.7A (VCC=3.0V, stop mode) Flash Memory Program/Erase Supply VCC=2.7 to 5.5V Voltage Program/Erase Endurance 100 times Operating Ambient Temperature -20 to 85C -40 to 85C (D Version) Package 20-pin plastic mold LSSOP NOTES: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 2 of 35 R8C/16 Group, R8C/17 Group 1. Overview Table 1.2 Performance Outline of the R8C/17 Group Item Performance CPU Number of Basic Instructions 89 instructions Minimum Instruction Execution 50ns(f(XIN)=20MHz, VCC=3.0 to 5.5V) Time 100ns(f(XIN)=10MHz, VCC=2.7 to 5.5V) Operating Mode Single-chip Address Space 1 Mbyte Memory Capacity See Table 1.4 R8C/17 Group Product Information Peripheral Port I/O : 13 pins (including LED drive port), Function Input : 2 pin LED drive port I/O port: 4 pins Timer Timer X: 8 bits x 1 channel, Timer Z: 8 bits x 1 channel (Each timer equipped with 8-bit prescaler) Timer C: 16 bits x 1 channel (Circuits of input capture and output compare) Serial Interface 1 channel Clock synchronous serial I/O, UART 1 channel I2C bus Interface (IIC)(1) A/D Converter 10-bit A/D converter: 1 circuit, 4 channels Watchdog Timer 15 bits x 1 channel (with prescaler) Reset start selectable, Count source protection mode Interrupt Internal: 9 factors, External: 4 factors, Software: 4 factors Priority level: 7 levels Clock Generation Circuit 2 circuits Main clock generation circuit (Equipped with a built-in feedback resistor) On-chip oscillator (high speed, low speed) Equipped with frequency adjustment function on highspeed on-chip oscillator Oscillation Stop Detection Main clock oscillation stop detection function Function Voltage Detection Circuit Included Power-on Reset Circuit Included Electric Supply Voltage VCC=3.0 to 5.5V (f(XIN)=20MHz) Characteristics VCC=2.7 to 5.5V (f(XIN)=10MHz) Power Consumption Typ. 9mA (VCC = 5.0V, f(XIN) = 20MHz) Typ. 5mA (VCC = 3.0V, f(XIN) = 10MHz) Typ.35A (VCC = 3.0V, wait mode, peripheral clock off) Typ. 0.7A (VCC = 3.0V, stop mode) Flash Memory Program/Erase Supply Voltage VCC=2.7 to 5.5V Program and Erase 10,000 times (Data flash) 1,000 times (Program ROM) Endurance Operating Ambient Temperature -20 to 85C -40 to 85C (D Version) Package 20-pin plastic mold LSSOP NOTES: 1. I2C bus is a trademark of Koninklijke Philips Electronics N. V. Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 3 of 35 R8C/16 Group, R8C/17 Group 1. Overview 1.3 Block Diagram Figure 1.1 shows a Block Diagram. 8 4 1 2 I/O port Peripheral Function Timer Port P1 Port P3 Port P4 A/D Converter (10 bits x 4 channels) UART or Clock Synchronous Serial I/O (8 bits x 1 channel) Timer X (8 bits) Timer Z (8 bits) Timer C (16 bits) System Clock Generator XIN-XOUT High-Speed On-Chip Oscillator Low-Speed On-Chip Oscillator I2C bus Interface Watchdog Timer (15 bits) R8C/Tiny Series CPU Core R0H R1H R2 R3 A0 A1 FB R0L R1L SB USP ISP INTB PC FLG Memory ROM(1) RAM(2) Multiplier NOTES: 1. ROM size depends on MCU type. 2. RAM size depends on MCU type. Figure 1.1 Block Diagram Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 4 of 35 R8C/16 Group, R8C/17 Group 1. Overview 1.4 Product Information Table 1.3 lists the Product Information of R8C/16 Group and Table 1.4 lists the Product Information of R8C/17 Group. Table 1.3 Product Information of R8C/16 Group ROM Capacity 8 Kbytes 12 Kbytes 16 Kbytes 8 Kbytes 12 Kbytes 16 Kbytes RAM Capacity 512 bytes 768 bytes 1 Kbyte 512 bytes 768 bytes 1 Kbyte Package Type PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A As of Jan 2006 Remarks Flash Memory Version Type No. R5F21162SP R5F21163SP R5F21164SP R5F21162DSP R5F21163DSP R5F21164DSP D Version Type No. R 5 F 21 16 4 D SP Package Type: SP : PLSP0020JB-A Grouping D : Operation Ambient Temperature -40C to 85C No Symbol : Operation Ambient Temperature -20C to 85C ROM Capacity 2 : 8KB 3 : 12KB 4 : 16KB R8C/16 Group R8C/Tiny Series Memory Type F : Flash Memory Version Renesas MCU Renesas Semiconductors Figure 1.2 Part Number, Memory Size and Package of R8C/16 Group Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 5 of 35 R8C/16 Group, R8C/17 Group 1. Overview Table 1.4 Type No. Product Information of R8C/17 Group ROM Capacity Program ROM Data flash 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 8 Kbytes 1 Kbyte x 2 12 Kbytes 1 Kbyte x 2 16 Kbytes 1 Kbyte x 2 RAM Capacity 512 bytes 768 bytes 1 Kbyte 512 bytes 768 bytes 1 Kbyte Package Type PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A PLSP0020JB-A As of Jan 2006 Remarks Flash Memory Version R5F21172SP R5F21173SP R5F21174SP R5F21172DSP R5F21173DSP R5F21174DSP D Version Type No. R 5 F 21 17 4 D SP Package Type: SP : PLSP0020JB-A Grouping D : Operation Ambient Temperature -40C to 85C No Symbol : Operating Ambient Temperature -20C to 85C ROM Capacity 2 : 8KB 3 : 12KB 4 : 16KB R8C/17 Group R8C/Tiny Series Memory Type F : Flash Memory Version Renesas MCU Renesas Semiconductors Figure 1.3 Part Number, Memory Size and Package of R8C/17 Group Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 6 of 35 R8C/16 Group, R8C/17 Group 1. Overview 1.5 Pin Assignments Figure 1.4 shows the PLSP0020JB-A Package Pin Assignment (top view). PIN Assignment (top view) P3_5/SCL/CMP1_2 P3_7/CNTR0 RESET XOUT/P4_7(1) VSS/AVSS XIN/P4_6 VCC MODE P4_5/INT0 P1_7/CNTR00/INT10 1 2 3 20 19 18 P3_4/SDA/CMP1_1 P3_3/TCIN/INT3/CMP1_0 P1_0/KI0/AN8/CMP0_0 P1_1/KI1/AN9/CMP0_1 AVCC/VREF P1_2/KI2/AN10/CMP0_2 P1_3/KI3/AN11/TZOUT P1_4/TXD0 P1_5/RXD0/CNTR01/INT11 P1_6/CLK0 R8C/16 Group R8C/17 Group 4 5 6 7 8 9 10 17 16 15 14 13 12 11 NOTES: 1. P4_7 is a port for the input. Package: PLSP0020JB-A(20P2F-A) Figure 1.4 PLSP0020JB-A Package Pin Assignment (top view) Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 7 of 35 R8C/16 Group, R8C/17 Group 1. Overview 1.6 Pin Description Table 1.5 lists the Pin Description and Table 1.6 lists the Pin Name Information by Pin Number. Table 1.5 Pin Description Pin Name VCC VSS I/O Type I I Description Apply 2.7V to 5.5V to the VCC pin. Apply 0V to the VSS pin Power supply input pins to A/D converter. Connect AVCC to VCC. Apply 0V to AVSS. Connect a capacitor between AVCC and AVSS. Input "L" on this pin resets the MCU Connect this pin to VCC via a resistor These pins are provided for the main clock generation circuit I/O. Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use an externally derived clock, input it to the XIN pin and leave the XOUT pin open. INT interrupt input pins Key input interrupt input pins Timer X I/O pin Timer X output pin Timer Z output pin Timer C input pin Timer C output pins Transfer clock I/O pin Serial data input pin Serial data output pin Clock I/O pin Data I/O pin Reference voltage input pin to A/D converter Connect VREF to VCC Analog input pins to A/D converter These are CMOS I/O ports. Each port contains an I/O select direction register, allowing each pin in that port to be directed for input or output individually. Any port set to input can select whether to use a pull-up resistor or not by program. P1_0 to P1_3 also function as LED drive ports. Port for input-only Function Power Supply Input Analog Power Supply AVCC Input AVSS Reset Input MODE Main Clock Input Main Clock Output RESET MODE XIN XOUT I I I O INT Interrupt Key Input Interrupt Timer X Timer Z Timer C INT0, INT1, INT3 KI0 to KI3 CNTR0 CNTR0 TZOUT TCIN CMP0_0 to CMP0_2, CMP1_0 to CMP1_2 I I I/O O O I O I/O I O I/O I/O I I I/O Serial Interface CLK0 RXD0 TXD0 I2C bus Interface (IIC) Reference Voltage Input A/D Converter I/O Port SCL SDA VREF AN8 to AN11 P1_0 to P1_7, P3_3 to P3_5, P3_7, P4_5 Input Port I: Input O: Output P4_6, P4_7 I/O: Input and output I Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 8 of 35 R8C/16 Group, R8C/17 Group 1. Overview Table 1.6 Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Name Information by Pin Number Control Pin Port P3_5 P3_7 RESET XOUT VSS/AVSS XIN VCC MODE P4_7 P4_6 I/O Pin of Peripheral Functions Serial I2C bus Timer Interface Interface CMP1_2 SCL CNTR0 Interrupt A/D Converter P4_5 P1_7 P1_6 P1_5 P1_4 P1_3 P1_2 AVCC/VREF P1_1 P1_0 P3_3 P3_4 INT0 INT10 INT11 KI3 KI2 KI1 KI0 INT3 CNTR00 CNTR01 TZOUT CMP0_2 CMP0_1 CMP0_0 TCIN/CMP1_0 CMP1_1 SDA CLK0 RXD0 TXD0 AN11 AN10 AN9 AN8 Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 9 of 35 R8C/16 Group, R8C/17 Group 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU Register. The CPU contains 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. Two sets of register banks are provided. b31 b15 b8b7 b0 R2 R3 R0H (high-order of R0) R1H (high-order of R1) R0L (low-order of R0) R1L (low-order of R1) Data Register (1) R2 R3 A0 A1 FB b19 b15 b0 Address Register (1) Frame Bass Register (1) INTBH INTBL Interrupt Table Register The 4-high order bits of INTB are INTBH and the 16-low bits of INTB are INTBL. b19 b0 PC Program Counter b15 b0 USP ISP SB b15 b0 User Stack Pointer Interrupt Stack Pointer Static Base Register FLG b15 b8 b7 b0 Flag Register IPL U I OBSZDC Carry Flag Debug Flag Zero Flag Sign Flag Register Bank Select Flag Overflow Flag Interrupt Enable Flag Stack Pointer Select Flag Reserved Bit Processor Interrupt Priority Level Reserved Bit NOTES: 1. A register bank comprises these registers. Two sets of register banks are provided. Figure 2.1 CPU Register Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 10 of 35 R8C/16 Group, R8C/17 Group 2. Central Processing Unit (CPU) 2.1 Data Registers (R0, R1, R2 and R3) R0 is a 16-bit register for transfer, arithmetic and logic operations. The same applies to R1 to R3. The R0 can be split into high-order bit (R0H) and low-order bit (R0L) to be used separately as 8-bit data registers. The same applies to R1H and R1L as R0H and R0L. R2 can be combined with R0 to be used as a 32-bit data register (R2R0). The same applies to R3R1 as R2R0. 2.2 Address Registers (A0 and A1) A0 is a 16-bit register for address register indirect addressing and address register relative addressing. They also are used for transfer, arithmetic and logic operations. The same applies to A1 as A0. A0 can be combined with A0 to be used as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is a 16-bit register for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is a 20-bit register indicates the start address of an interrupt vector table. 2.5 Program Counter (PC) PC, 20 bits wide, indicates the address of an instruction to be executed. 2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) The stack pointer (SP), USP and ISP, are 16 bits wide each. The U flag of FLG is used to switch between USP and ISP. 2.7 Static Base Register (SB) SB is a 16-bit register for SB relative addressing. 2.8 Flag Register (FLG) FLG is a 11-bit register indicating the CPU state. 2.8.1 Carry Flag (C) The C flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic logic unit. 2.8.2 Debug Flag (D) The D flag is for debug only. Set to "0". 2.8.3 Zero Flag (Z) The Z flag is set to "1" when an arithmetic operation resulted in 0; otherwise, "0". 2.8.4 Sign Flag (S) The S flag is set to "1" when an arithmetic operation resulted in a negative value; otherwise, "0". 2.8.5 Register Bank Select Flag (B) The register bank 0 is selected when the B flag is "0". The register bank 1 is selected when this flag is set to "1". 2.8.6 Overflow Flag (O) The O flag is set to "1" when the operation resulted in an overflow; otherwise, "0". Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 11 of 35 R8C/16 Group, R8C/17 Group 2. Central Processing Unit (CPU) 2.8.7 Interrupt Enable Flag (I) The I flag enables a maskable interrupt. An interrupt is disabled when the I flag is set to "0", and are enabled when the I flag is set to "1". The I flag is set to "0" when an interrupt request is acknowledged. 2.8.8 Stack Pointer Select Flag (U) ISP is selected when the U flag is set to "0", USP is selected when the U flag is set to "1". The U flag is set to "0" when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL, 3 bits wide, assigns processor interrupt priority levels from level 0 to level 7. If a requested interrupt has greater priority than IPL, the interrupt is enabled. 2.8.10 Reserved Bit When write to this bit, set to "0". When read, its content is indeterminate. Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 12 of 35 R8C/16 Group, R8C/17 Group 3. Memory 3. 3.1 Memory R8C/16 Group Figure 3.1 is a Memory Map of the R8C/16 group. The R8C/16 group provides 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM is allocated lower addresses beginning with address 0FFFFh. For example, a 16Kbyte internal ROM is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1Kbyte internal RAM is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but for calling subroutines and stacks when interrupt request is acknowledged. Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated them. All addresses, which have nothing allocated within the SFR, are reserved area and cannot be accessed by users. 00000h SFR (See 4. Special Function Register (SFR)) 002FFh 00400h Internal RAM 0XXXXh 0FFDCh Undefined Instruction Overflow BRK Instruction Address Match Single Step Watchdog Timer * Oscillation Stop Detection * Voltage Monitor 2 0YYYYh Internal ROM 0FFFFh 0FFFFh Address Break (Reserved) Reset Expansion Area FFFFFh NOTES: 1. Blank spaces are reserved. No access is allowed. Internal ROM Part Number R5F21164SP, R5F21164DSP R5F21163SP, R5F21163DSP R5F21162SP, R5F21162DSP Size 16 Kbytes 12 Kbytes 8 Kbytes 0YYYYh 0C000h 0D000h 0E000h Internal RAM Size 1 Kbyte 768 bytes 512 bytes 0XXXXh 007FFh 006FFh 005FFh Figure 3.1 Memory Map of R8C/16 Group Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 13 of 35 R8C/16 Group, R8C/17 Group 3. Memory 3.2 R8C/17 Group Figure 3.2 is a memory map of the R8C/17 group. The R8C/17 group provides 1-Mbyte address space from addresses 00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses beginning with address 0FFFFh. For example, a 16-Kbyte internal ROM is allocated addresses 0C000h to 0FFFFh. The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine. The internal ROM (data flash) is allocated addresses 02400h to 02BFFh. The internal RAM is allocated higher addresses beginning with address 00400h. For example, a 1Kbyte internal RAM is allocated addresses 00400h to 007FFh. The internal RAM is used not only for storing data but for calling subroutines and stacks when interrupt request is acknowledged. Special function registers (SFR) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated them. All addresses, which have nothing allocated within the SFR, are reserved area and cannot be accessed by users. 00000h SFR (See 4. Special Function Register (SFR)) 002FFh 00400h Internal RAM 0XXXXh 02400h 02BFFh Internal ROM (Data flash)(1) 0FFDCh Undefined Instruction Overflow BRK Instruction Address Match Single Step Watchdog Timer * Oscillation Stop Detection * Voltage Monitor 2 0YYYYh Internal ROM (Program ROM) 0FFFFh 0FFFFh Address Break (Reserved) Reset Expansion Area FFFFFh NOTES: 1. The data flash block A (1 Kbyte) and block B (1 Kbyte) are shown. 2. Blank spaces are reserved. No access is allowed. Internal ROM Part Number R5F21174SP, R5F21174DSP R5F21173SP, R5F21173DSP R5F21172SP, R5F21172DSP Size 16 Kbytes 12 Kbytes 8 Kbytes 0YYYYh 0C000h 0D000h 0E000h Internal RAM Size 1 Kbyte 768 bytes 512 bytes 0XXXXh 007FFh 006FFh 005FFh Figure 3.2 Memory Map of R8C/17 Group Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 14 of 35 R8C/16 Group, R8C/17 Group 4. Special Function Register (SFR) 4. Special Function Register (SFR) SFR (Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.4 list the SFR information. Table 4.1 SFR Information(1)(1) Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Register Symbol After Reset Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System Clock Control Register 1 Address Match Interrupt Enable Register Protect Register Oscillation Stop Detection register Watchdog Timer Reset Register Watchdog Timer Start Register Watchdog Timer Control Register Address Match Interrupt Register 0 PM0 PM1 CM0 CM1 AIER PRCR OCD WDTR WDTS WDC RMAD0 00h 00h 01101000b 00100000b 00h 00h 00000100b XXh XXh 00011111b 00h 00h X0h 00h 00h X0h Address Match Interrupt Register 1 RMAD1 Count Source Protection Mode Register INT0 Input Filter Select Register High-Speed On-Chip Oscillator Control Register 0 High-Speed On-Chip Oscillator Control Register 1 High-Speed On-Chip Oscillator Control Register 2 CSPR INT0F HRA0 HRA1 HRA2 00h 00h 00h When shipping 00h Voltage Detection Register 1(2) Voltage Detection Register 2(2) VCA1 VCA2 00001000b 00h(3) 01000000b(4) Voltage Monitor 1 Circuit Control Register (2) Voltage Monitor 2 Circuit Control Register (5) VW1C VW2C 0000X000b(3) 0100X001b(4) 00h X: Undefined NOTES: 1. Blank spaces are reserved. No access is allowed. 2. Software reset, the watchdog timer reset or the voltage monitor 2 reset does not affect this register. 3. Owing to Hardware reset. 4. Owing to Power-on reset or the voltage monitor 1 reset. 5. Software reset, the watchdog timer reset or the voltage monitor 2 reset does not affect the b2 and b3. Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 15 of 35 R8C/16 Group, R8C/17 Group Table 4.2 Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h 0061h 0062h 0063h 0064h 0065h 0066h 0067h 0068h 0069h 006Ah 006Bh 006Ch 006Dh 006Eh 006Fh 0070h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh 4. Special Function Register (SFR) SFR Information(2)(1) Register Symbol After reset Key Input Interrupt Control Register A/D Conversion Interrupt Control Register IIC Interrupt Control Register Compare 1 Interrupt Control Register UART0 Transmit Interrupt Control Register UART0 Receive Interrupt Control Register KUPIC ADIC IIC2AIC CMP1IC S0TIC S0RIC XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b Timer X Interrupt Control Register Timer Z Interrupt Control Register INT1 Interrupt Control Register INT3 Interrupt Control Register Timer C Interrupt Control Register Compare 0 Interrupt Control Register INT0 Interrupt Control Register TXIC TZIC INT1IC INT3IC TCIC CMP0IC INT0IC XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XXXXX000b XX00X000b X: Undefined NOTES: 1. Blank spaces are reserved. No access is allowed. Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 16 of 35 R8C/16 Group, R8C/17 Group Table 4.3 Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh 4. Special Function Register (SFR) SFR Information(3)(1) Register Timer Z Mode Register TZMR Symbol 00h After Reset Timer Z Waveform Output Control Register Prescaler Z Register Timer Z Secondary Register Timer Z Primary Register PUM PREZ TZSC TZPR 00h FFh FFh FFh Timer Z Output Control Register Timer X Mode Register Prescaler X Register Timer X Register Timer Count Source Setting Register Timer C Register TZOC TXMR PREX TX TCSS TC 00h 00h FFh FFh 00h 00h 00h External Input Enable Register Key Input Enable Register Timer C Control Register 0 Timer C Control Register 1 Capture, Compare 0 Register Compare 1 Register UART0 Transmit/Receive Mode Register UART0 Bit Rate Register UART0 Transmit Buffer Register UART0 Transmit/Receive Control Register 0 UART0 Transmit/Receive Control Register 1 UART0 Receive Buffer Register INTEN KIEN TCC0 TCC1 TM0 TM1 U0MR U0BRG U0TB U0C0 U0C1 U0RB 00h 00h 00h 00h 00h 00h(2) FFh FFh 00h XXh XXh XXh 00001000b 00000010b XXh XXh UART Transmit/Receive Control Register 2 UCON 00h IIC bus Control Register 1 IIC bus Control Register 2 IIC bus Mode Register IIC bus Interrupt Enable Register IIC bus Status Register Slave Address Register IIC bus Transmit Data Register IIC bus Receive Data Register ICCR1 ICCR2 ICMR ICIER ICSR SAR ICDRT ICDRR 00h 7Dh 18h 00h 00h 00h FFh FFh X: Undefined NOTES: 1. Blank spaces are reserved. No access is allowed. 2. When output compare mode (the TCC13 bit in the TCC1 register = 1) is selected, the value after reset is "FFFFh". Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 17 of 35 R8C/16 Group, R8C/17 Group Table 4.4 Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00CEh 00CFh 00D0h 00D1h 00D2h 00D3h 00D4h 00D5h 00D6h 00D7h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h 00E2h 00E3h 00E4h 00E5h 00E6h 00E7h 00E8h 00E9h 00EAh 00EBh 00ECh 00EDh 00EEh 00EFh 00F0h 00F1h 00F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh 01B3h 01B4h 01B5h 01B6h 01B7h 0FFFFh 4. Special Function Register (SFR) SFR Information(4)(1) Register A/D Register AD Symbol XXh XXh After reset A/D Control Register 2 A/D Control Register 0 A/D Control Register 1 ADCON2 ADCON0 ADCON1 00h 00000XXXb 00h Port P1 Register Port P1 Direction Register Port P3 Register Port P3 Direction Register Port P4 Register Port P4 Direction Register P1 PD1 P3 PD3 P4 PD4 XXh 00h XXh 00h XXh 00h Pull-Up Control Register 0 Pull-Up Control Register 1 Port P1 Drive Capacity Control Register Timer C Output Control Register Flash Memory Control Register 4 Flash Memory Control Register 1 Flash Memory Control Register 0 Optional Function Select Register PUR0 PUR1 DRR TCOUT FMR4 FMR1 FMR0 OFS 00XX0000b XXXXXX0Xb 00h 00h 01000000b 1000000Xb 00000001b (2) X: Undefined NOTES: 1. Blank columns, 0100h to 01B2h and 01B8h to 02FFh are all reserved. No access is allowed. 2. The OFS register cannot be changed by program. Use a flash programmer to write to it. Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 18 of 35 R8C/16 Group, R8C/17 Group 5. Electrical Characteristics 5. Electrical Characteristics Table 5.1 Symbol VCC AVCC VI VO Pd Topr Tstg Supply Voltage Analog Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Ambient Temperature Storage Temperature Topr = 25C Absolute Maximum Ratings Parameter Condition VCC = AVCC VCC = AVCC Rated value -0.3 to 6.5 -0.3 to 6.5 -0.3 to VCC+0.3 -0.3 to VCC+0.3 300 -20 to 85 / -40 to 85 (D version) -65 to 150 Unit V V V V mW C C Table 5.2 Symbol VCC AVCC VSS AVSS VIH VIL IOH(sum) Recommended Operating Conditions Parameter Supply Voltage Analog Supply Voltage Supply Voltage Analog Supply Voltage Input "H" Voltage Input "L" Voltage Peak Sum Output "H" Current Sum of All Pins IOH (peak) Conditions Standard Min. 2.7 - - - 0.8VCC 0 - Typ. - VCC(3) 0 0 - - - Max. 5.5 - - - VCC 0.2VCC -60 Unit V V V V V V mA IOH(peak) IOH(avg) IOL(sum) Peak Output "H" Current Average Output "H" Current Peak Sum Output "L" Currents Peak Output "L" Currents Average Output "L" Current Sum of All Pins IOL (peak) Except P1_0 to P1_3 P1_0 to P1_3 Except P1_0 to P1_3 P1_0 to P1_3 Drive Capacity HIGH Drive Capacity LOW 3.0V VCC 5.5V 2.7V VCC < 3.0V Drive Capacity HIGH Drive Capacity LOW - - - - - - -10 -5 60 mA mA mA IOL(peak) - - - - - - 0 0 - - - - - - - - 10 30 10 5 15 5 20 10 mA mA mA mA mA mA MHz MHz IOL(avg) f(XIN) Main Clock Input Oscillation Frequency NOTES: 1. VCC = AVCC = 2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. The typical values when average output current is 100ms. 3. Hold VCC = AVCC. Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 19 of 35 R8C/16 Group, R8C/17 Group 5. Electrical Characteristics Table 5.3 Symbol - - A/D Converter Characteristics Parameter Resolution Absolute Accuracy 10-Bit Mode 8-Bit Mode 10-Bit Mode 8-Bit Mode Vref = VCC AD = 10MHz, Vref = VCC = 5.0V AD = 10MHz, Vref = VCC = 5.0V AD = 10MHz, Vref = VCC = 3.3V(3) AD = 10MHz, Vref = VCC = 3.3V(3) Vref = VCC AD = 10MHz, Vref = VCC = 5.0V AD = 10MHz, Vref = VCC = 5.0V 8-Bit Mode Conditions Standard Min. - - - - - 10 3.3 2.8 - 0 0.25 1 Without Sample & Hold With Sample & Hold Typ. - - - - - - - - VCC(4) - - - Max. 10 3 2 5 2 40 - - - Vref 10 10 Unit Bits LSB LSB LSB LSB k s s V V MHz MHz Rladder tconv Vref VIA - Resistor Ladder Conversion Time 10-Bit Mode Reference voltage Analog Input Voltage A/D Operating Clock Frequency(2) NOTES: 1. VCC = AVCC = 2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. If f1 exceeds 10MHz, divide the f1 and hold A/D operating clock frequency (AD) 10MHz or below. 3. If the AVcc is less than 4.2V, divide the f1 and hold A/D operating clock frequency (AD) f1/2 or below. 4. Hold VCC = Vref P1 P3 P4 30pF Figure 5.1 Port P1, P3 and P4 Measurement Circuit Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 20 of 35 R8C/16 Group, R8C/17 Group 5. Electrical Characteristics Table 5.4 Symbol - Flash Memory (Program ROM) Electrical Characteristics Parameter Program/Erase Endurance(2) Conditions R8C/16 Group R8C/17 Group Standard Min. 100(3) 1,000(3) - - - 10 2.7 2.7 0 Ambient temperature = 55 C 20 Typ. - - 50 0.4 - - - - - - Max. - - 400 9 8 - 5.5 5.5 60 - Unit times times s s ms ms V V C year - - td(SR-ES) - - - - - Byte Program Time Block Erase Time Time Delay from Suspend Request until Erase Suspend Erase Suspend Request Interval Program, Erase Voltage Read Voltage Program, Erase Temperature Data Hold Time(7) VCC = 5.0 V at Topr = 25 C VCC = 5.0 V at Topr = 25 C NOTES: 1. VCC = AVcc = 2.7 to 5.5V at Topr = 0 to 60 C, unless otherwise specified. 2. Definition of program and erase The program and erase endurance shows an erase endurance for every block. If the program and erase endurance is "n" times (n = 100, 10000), "n" times erase can be performed for every block. For example, if performing 1-byte write to the distinct addresses on Block A of 1Kbyte block 1,024 times and then erasing that block, program and erase endurance is counted as one time. However, do not perform multiple programs to the same address for one time ease.(disable overwriting). 3. Endurance to guarantee all electrical characteristics after program and erase.(1 to "Min." value can be guaranateed). 4. In the case of a system to execute multiple programs, perform one erase after programming as reducing effective reprogram endurance not to leave blank area as possible such as programming write addresses in turn. If programming a set of 16 bytes, programming up to 128 sets and then erasing them one time can reduce effective reprogram endurance. Additionally, averaging erase endurance for Block A and B can reduce effective reprogram endurance more. To leave erase endurance for every block as information and determine the restricted endurance are recommended. 5. If error occurs during block erase, attempt to execute the clear status register command, then the block erase command at least three times until the erase error does not occur. 6. Customers desiring Program/Erase failure rate information should contact their Renesas technical support representative. 7. The data hold time incudes time that the power supply is off or the clock is not supplied. Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 21 of 35 R8C/16 Group, R8C/17 Group 5. Electrical Characteristics Table 5.5 Symbol - - Flash Memory (Data flash Block A, Block B) Electrical Characteristics Parameter Program/Erase Endurance(2) Byte Program Time (Program/Erase Endurance 1,000 Times) Byte Program Time (Program/Erase Endurance > 1,000 Times) Block Erase Time (Program/Erase Endurance 1,000 Times) VCC = 5.0 V at Topr = 25 C VCC = 5.0 V at Topr = 25 C VCC = 5.0 V at Topr = 25 C VCC = 5.0 V at Topr = 25 C Conditions Standard Min. 10,000(3) - - - - - 10 2.7 2.7 -20(8) Ambient temperature = 55 C 20 Typ. - 50 65 0.2 0.3 - - - - - - Max. - 400 - 9 - 8 - 5.5 5.5 85 - Unit times s s s s ms ms V V C year - td(SR-ES) - - - - - Block Erase Time (Program/Erase Endurance > 1,000 Times) Time Delay from Suspend Request until Erase Suspend Erase Suspend Request Interval Program, Erase Voltage Read Voltage Program, Erase Temperature Data Hold Time(9) NOTES: 1. VCC = AVcc = 2.7 to 5.5V at Topr = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. Definition of program and erase The program and erase endurance shows an erase endurance for every block. If the program and erase endurance is "n" times (n = 100, 10000), "n" times erase can be performed for every block. For example, if performing 1-byte write to the distinct addresses on Block A of 1Kbyte block 1,024 times and then erasing that block, program and erase endurance is counted as one time. However, do not perform multiple programs to the same address for one time ease.(disable overwriting). 3. Endurance to guarantee all electrical characteristics after program and erase.(1 to "Min." value can be guaranateed). 4. Standard of Block A and Block B when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times are the same as that in program area. 5. In the case of a system to execute multiple programs, perform one erase after programming as reducing effective reprogram endurance not to leave blank area as possible such as programming write addresses in turn. If programming a set of 16 bytes, programming up to 128 sets and then erasing them one time can reduce effective reprogram endurance. Additionally, averaging erase endurance for Block A and B can reduce effective reprogram endurance more. To leave erase endurance for every block as information and determine the restricted endurance are recommended. 6. If error occurs during block erase, attempt to execute the clear status register command, then the block erase command at least three times until the erase error does not occur. 7. Customers desiring Program/Erase failure rate information should contact their Renesas technical support representative. 8. -40 C for D version. 9. The data hold time incudes time that the power supply is off or the clock is not supplied. Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 22 of 35 R8C/16 Group, R8C/17 Group 5. Electrical Characteristics Erase-Suspend Request (Maskable interrupt Request) FMR46 td(SR-ES) Figure 5.2 Time delay from Suspend Request until Erase Suspend Table 5.6 Symbol Vdet1 - td(E-A) Vccmin Voltage Detection 1 Circuit Electrical Characteristics Parameter Voltage Detection Level(3) Voltage Detection Circuit Self Power Consumption Waiting Time until Voltage Detection Circuit Operation Starts(2) Microcomputer Operating Voltage Minimum Value VCA26 = 1, VCC = 5.0V Condition Standard Min. 2.70 - - 2.7 Typ. 2.85 600 - - Max. 3.00 - 100 - Unit V nA s V NOTES: 1. The measurement condition is VCC = AVCC = 2.7V to 5.5V and Topr = -40C to 85 C. 2. Necessary time until the voltage detection circuit operates when setting to "1" again after setting the VCA26 bit in the VCA2 register to "0". 3. Hold Vdet2 > Vdet1. Table 5.7 Symbol Vdet2 - - td(E-A) Voltage Detection 2 Circuit Electrical Characteristics Parameter Voltage Detection Level(4) Voltage Monitor 2 Interrupt Request Generation Time(2) Voltage Detection Circuit Self Power Consumption Waiting Time until Voltage Detection Circuit Operation Starts(3) VCA27 = 1, VCC = 5.0V Condition Standard Min. 3.00 - - - Typ. 3.30 40 600 - Max. 3.60 - - 100 Unit V s nA s NOTES: 1. The measurement condition is VCC = AVCC = 2.7V to 5.5V and Topr = -40C to 85 C. 2. Time until the voltage monitor 2 interrupt request is generated since the voltage passes Vdet1. 3. Necessary time until the voltage detection circuit operates when setting to "1" again after setting the VCA27 bit in the VCA2 register to "0". 4. Hold Vdet2 > Vdet1. Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 23 of 35 R8C/16 Group, R8C/17 Group 5. Electrical Characteristics Table 5.8 Symbol Vpor2 Reset Circuit Electrical Characteristics (When Using Voltage Monitor 1 Reset ) Parameter Power-On Reset Valid Voltage Condition Min. -20C Topr < 85C - - Standard Typ. - - Max. Vdet1 100 V ms Unit tw(Vpor2-Vdet1) Supply Voltage Rising Time When Power-On Reset is -20C Topr < 85C, Deasserted(1) tw(por2) 0s(3) NOTES: 1. This condition is not applicable when using with Vcc 1.0V. 2. When turning power on after the time to hold the external power below effective voltage (Vpor1) exceeds10s, refer to Table 5.9 Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset). 3. tw(por2) is time to hold the external power below effective voltage (Vpor2). Table 5.9 Symbol Vpor1 tw(Vpor1-Vdet1) tw(Vpor1-Vdet1) tw(Vpor1-Vdet1) tw(Vpor1-Vdet1) Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset) Parameter Power-On Reset Valid Voltage Supply Voltage Rising Time When Power-On Reset is Deasserted Supply Voltage Rising Time When Power-On Reset is Deasserted Supply Voltage Rising Time When Power-On Reset is Deasserted Supply Voltage Rising Time When Power-On Reset is Deasserted Condition Min. -20C Topr < 85C 0C Topr 85C, tw(por1) 10s(2) -20C Topr < 0C, tw(por1) 30s(2) -20C Topr < 0C, tw(por1) 10s(2) 0C Topr 85C, tw(por1) 1s(2) - - - - - Standard Typ. - - - - - Max. 0.1 100 100 1 0.5 V ms ms ms ms Unit NOTES: 1. When not using the voltage monitor 1 reset, use with Vcc 2.7V. 2. tw(por1) is time to hold the external power below effective voltage (Vpor1). Vdet1(3) Vccmin Vpor2 Vpor1 tw(por1) tw(Vpor1-Vdet1) Sampling Time(1, 2) tw(por2) tw(Vpor2-Vdet1) Vdet1(3) Internal Reset Signal ("L" Valid) 1 x 32 fRING-S 1 x 32 fRING-S NOTES: 1. Hold the voltage of the microcomputer operation voltage range (Vccmin or above) within sampling time. 2. A sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual for details. 3. Vdet1 indicates the voltage detection level of the voltage detection 1 circuit. Refer to 6. Voltage Detection Circuit of Hardware Manual for details. Figure 5.3 Reset Circuit Electrical Characteristics Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 24 of 35 R8C/16 Group, R8C/17 Group 5. Electrical Characteristics Table 5.10 Symbol - - High-speed On-Chip Oscillator Circuit Electrical Characteristics Parameter High-Speed On-Chip Oscillator Frequency When the Reset is Deasserted High-Speed On-Chip Oscillator Frequency Temperature * Supplay Voltage Dependence Condition VCC = 5.0V, Topr = 25 C 0 to +60 C / 5 V 5 %(2) -20 to +85 C / 2.7 to 5.5 V(2) -40 to +85 C / 2.7 to 5.5 V(2) Standard Min. - 7.44 7.04 6.80 Typ. 8 - - - Max. - 8.56 8.96 9.20 Unit MHz MHz MHz MHz NOTES: 1. The measurement condition is VCC = AVCC = 5.0V and Topr = 25 C. 2. The standard value shows when the HRA1 register is assumed as the value in shipping and the HRA2 register value is set to 00h. Table 5.11 Symbol td(P-R) td(R-S) Power Supply Circuit Timing Characteristics Parameter Time for Internal Power Supply Stabilization during Power-On(2) STOP Exit Time(3) Condition Standard Min. 1 - Typ. - - Max. 2000 150 Unit s s NOTES: 1. The measurement condition is VCC = AVCC = 2.7 to 5.5V and Topr = 25 C. 2. Waiting time until the internal power supply generation circuit stabilizes during power-on. 3. Time until CPU clock supply starts since the interrupt is acknowledged to exit stop mode. Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 25 of 35 R8C/16 Group, R8C/17 Group 5. Electrical Characteristics Table 5.12 Symbol tSCL tSCLH tSCLL tsf tSP tBUF tSTAH tSTAS tSTOS tSDAS tSDAH Timing Requirements of I2C bus Interface (IIC) (1) Parameter SCL Input Cycle Time SCL Input "H" Width SCL Input "L" Width SCL, SDA Input Fall Time SCL, SDA Input Spike Pulse Rejection Time SDA Input Bus-Free Time Start Condition Input Hold Time Retransmit Start Condition Input SetUp Time Stop Condition Input SetUp Time Data Input SetUp Time Data Input Hold Time Condition Standard Min. 12tCYC+ 600(2) 3tCYC+ 300(2) 5tCYC+ 300(2) - - 5tCYC(2) 3tCYC(2) 3tCYC(2) 3tCYC(2) 1tCYC+20(2) 0 Typ. - - - - - - - - - - - Max. - - - 300 1tCYC(2) - - - - - - Unit ns ns ns ns ns ns ns ns ns ns ns NOTES: 1. VCC = AVCC = 2.7 to 5.5V, VSS = 0V and Topr = -20 to 85 C / -40 to 85 C, unless otherwise specified. 2. 1tCYC=1/f1(s) VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL P(2) S(1) tsf tSCLL tSCL tSDAH Sr(3) tSDAS P(2) NOTES: 1. Start condition 2. Stop condition 3. Retransmit "start" condition Figure 5.4 I/O Timing of I2C bus Interface (IIC) Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 26 of 35 R8C/16 Group, R8C/17 Group 5. Electrical Characteristics Table 5.13 Symbol VOH Electrical Characteristics (1) [VCC = 5V] Parameter Condition IOH = -5mA IOH = -200A XOUT Drive capacity HIGH Drive capacity LOW IOH = -1mA IOH = -500A Standard Min. VCC - 2.0 VCC - 0.3 VCC - 2.0 VCC - 2.0 - - IOL = 15mA IOL = 5mA IOL = 200A IOL = 1mA IOL = 500A - - - - - 0.2 Typ. - - - - - - - - - - - - Max. VCC VCC VCC VCC 2.0 0.45 2.0 2.0 0.45 2.0 2.0 1.0 Unit V V V V V V V V V V V V Output "H" Voltage Except XOUT VOL Output "L" Voltage Except P1_0 to P1_3, XOUT P1_0 to P1_3 IOL = 5mA IOL = 200A Drive capacity HIGH Drive capacity LOW Drive capacity LOW XOUT Drive capacity HIGH Drive capacity LOW VT+-VT- Hysteresis INT0, INT1, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RXD0 RESET VI = 5V VI = 0V VI = 0V XIN 0.2 - - 30 - 40 During stop mode 2.0 - - - 50 1.0 125 - 2.2 5.0 -5.0 167 - 250 - V A A k M kHz V IIH IIL RfXIN fRING-S VRAM Input "H" current Input "L" current Feedback Resistance RAM Hold Voltage RPULLUP Pull-Up Resistance Low-Speed On-Chip Oscillator Frequency NOTES: 1. VCC = AVCC = 4.2 to 5.5V at Topr = -20 to 85 C / -40 to 85 C, f(XIN)=20MHz, unless otherwise specified. Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 27 of 35 R8C/16 Group, R8C/17 Group 5. Electrical Characteristics Table 5.14 Symbol ICC Electrical Characteristics (2) [Vcc = 5V] (Topr = -40 to 85 C, unless otherwise specified.) Parameter Condition High-Speed Mode XIN = 20MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz No division XIN = 16MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz No division XIN = 10MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz No division MediumSpeed Mode XIN = 20MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz Divide-by-8 XIN = 16MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz Divide-by-8 XIN = 10MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz Divide-by-8 High-Speed On-Chip Oscillator Mode Main clock off High-speed on-chip oscillator on=8MHz Low-speed on-chip oscillator on=125kHz No division Main clock off High-speed on-chip oscillator on=8MHz Low-speed on-chip oscillator on=125kHz Divide-by-8 Low-Speed On-Chip Oscillator Mode Wait Mode Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz Divide-by-8 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz While a WAIT instruction is executed Peripheral clock operation VCA26 = VCA27 = 0 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz While a WAIT instruction is executed Peripheral clock off VCA26 = VCA27 = 0 Main clock off, Topr = 25 C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA26 = VCA27 = 0 Standard Min. - Typ. 9 Max. 15 Unit mA Power Supply Current (VCC=3.3 to 5.5V) In single-chip mode, the output pins are open and other pins are VSS - 8 14 mA - 5 - mA - 4 - mA - 3 - mA - 2 - mA - 4 8 mA - 1.5 - mA - 470 900 A - 40 80 A Wait Mode - 38 76 A Stop Mode - 0.8 3.0 A Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 28 of 35 R8C/16 Group, R8C/17 Group 5. Electrical Characteristics Timing Requirements (Unless otherwise specified: VCC = 5V, VSS = 0V at Topr = 25 C) [ VCC = 5V ] Table 5.15 Symbol tc(XIN) tWH(XIN) tWL(XIN) XIN Input Cycle Time XIN Input "H" Width XIN Input "L" Width XIN Input Parameter Standard Min. 50 25 25 Max. - - - Unit ns ns ns Table 5.16 Symbol tc(CNTR0) tWH(CNTR0) tWL(CNTR0) CNTR0 Input, CNTR1 Input, INT1 Input Parameter CNTR0 Input Cycle Time CNTR0 Input "H" Width CNTR0 input "L" Width Standard Min. 100 40 40 Max. - - - Unit ns ns ns Table 5.17 Symbol tc(TCIN) tWH(TCIN) tWL(TCIN) TCIN Input, INT3 Input Parameter TCIN Input Cycle Time TCIN Input "H" Width TCIN input "L" Width Standard Min. 400(1) 200(2) 200(2) Max. - - - Unit ns ns ns NOTES: 1. When using Timer C input capture mode, adjust the cycle time ( 1/ Timer C count source frequency x 3) or above. 2. When using Timer C input capture mode, adjust the width ( 1/ Timer C count source frequency x 1.5) or above. Table 5.18 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Serial Interface Parameter CLKi Input Cycle Time CLKi Input "H" Width CLKi Input "L" Width TXDi Output Delay Time TXDi Hold Time RXDi Input Setup Time RCDi Input Hold Time Standard Min. 200 100 100 - 0 50 90 Max. - - - 50 - - - Unit ns ns ns ns ns ns ns Table 5.19 Symbol tW(INH) tW(INL) External Interrupt INT0 Input Parameter INT0 Input "H" Width INT0 Input "L" Width Standard Min. 250(1) 250(2) Max. - - Unit ns ns NOTES: 1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH width to the greater value, either (1/ digital filter clock frequency x 3) or the minimum value of standard. 2. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW width to the greater value, either (1/ digital filter clock frequency x 3) or the minimum value of standard. Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 29 of 35 R8C/16 Group, R8C/17 Group 5. Electrical Characteristics VCC = 5V tc(CNTR0) tWH(CNTR0) CNTR0 Input tWL(CNTR0) tc(TCIN) tWH(TCIN) TCIN Input tWL(TCIN) tc(XIN) tWH(XIN) XIN Input tWL(XIN) tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TxDi td(C-Q) RxDi tW(INL) INTi Input tW(INH) tsu(D-C) th(C-D) Figure 5.5 Timing Diagram When VCC = 5V Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 30 of 35 R8C/16 Group, R8C/17 Group 5. Electrical Characteristics Table 5.20 Symbol VOH Electrical Characteristics (3) [VCC = 3V] Parameter Condition IOH = -1mA Drive capacity HIGH Drive capacity LOW IOH = -0.1mA IOH = -50A Standard Min. VCC - 0.5 VCC - 0.5 VCC - 0.5 - IOL = 2mA IOL = 1mA IOL = 0.1mA IOL = 50A - - - - 0.2 Typ. - - - - - - - - - Max. VCC VCC VCC 0.5 0.5 0.5 0.5 0.5 0.8 Unit V V V V V V V V V Output "H" Voltage Except XOUT XOUT VOL Output "L" Voltage Except P1_0 to P1_3, XOUT P1_0 to P1_3 IOL = 1mA Drive capacity HIGH Drive capacity LOW XOUT Drive capacity HIGH Drive capacity LOW VT+-VT- Hysteresis INT0, INT1, INT3, KI0, KI1, KI2, KI3, CNTR0, CNTR1, TCIN, RXD0 RESET VI = 3V VI = 0V VI = 0V XIN 0.2 - - 66 - 40 During stop mode 2.0 - - - 160 3.0 125 - 1.8 4.0 -4.0 500 - 250 - V A A k M kHz V IIH IIL RfXIN fRING-S VRAM Input "H" Current Input "L" Current Feedback Resistance RAM Hold Voltage RPULLUP Pull-Up Resistance Low-Speed On-Chip Oscillator Frequency NOTES: 1. VCC = AVCC = 2.7 to 3.3V at Topr = -20 to 85 C / -40 to 85 C, f(XIN)=10MHz, unless otherwise specified. Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 31 of 35 R8C/16 Group, R8C/17 Group 5. Electrical Characteristics Table 5.21 Symbol ICC Electrical Characteristics (4) [Vcc = 3V] (Topr = -40 to 85 C, unless otherwise specified.) Parameter Condition High-Speed Mode XIN = 20MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz No division XIN = 16MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz No division XIN = 10MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz No division MediumSpeed Mode XIN = 20MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz Divide-by-8 XIN = 16MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz Divide-by-8 XIN = 10MHz (square wave) High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz Divide-by-8 High-Speed On-Chip Oscillator Mode Main clock off High-speed on-chip oscillator on=8MHz Low-speed on-chip oscillator on=125kHz No division Main clock off High-speed on-chip oscillator on=8MHz Low-speed on-chip oscillator on=125kHz Divide-by-8 Low-Speed On-Chip Oscillator Mode Wait Mode Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz Divide-by-8 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz While a WAIT instruction is executed Peripheral clock operation VCA26 = VCA27 = 0 Main clock off High-speed on-chip oscillator off Low-speed on-chip oscillator on=125kHz While a WAIT instruction is executed Peripheral clock off VCA26 = VCA27 = 0 Main clock off, Topr = 25 C High-speed on-chip oscillator off Low-speed on-chip oscillator off CM10 = 1 Peripheral clock off VCA26 = VCA27 = 0 Standard Min. - Typ. 8 Max. 13 Unit mA Power Supply Current (VCC=2.7 to 3.3V) In single-chip mode, the output pins are open and other pins are VSS - 7 12 mA - 5 - mA - 3 - mA - 2.5 - mA - 1.6 - mA - 3.5 7.5 mA - 1.5 - mA - 420 800 A - 37 74 A Wait Mode - 35 70 A Stop Mode - 0.7 3.0 A Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 32 of 35 R8C/16 Group, R8C/17 Group 5. Electrical Characteristics Timing requirements (Unless otherwise specified: VCC = 3V, VSS = 0V at Topr = 25 C) [VCC = 3V] Table 5.22 Symbol tc(XIN) tWH(XIN) tWL(XIN) XIN Input Cycle Time XIN Input "H" Width XIN Input "L" Width XIN Input Parameter Standard Min. 100 40 40 Max. - - - Unit ns ns ns Table 5.23 Symbol tc(CNTR0) tWH(CNTR0) tWL(CNTR0) CNTR0 Input, CNTR1 Input, INT1 Input Parameter CNTR0 Input Cycle Time CNTR0 Input "H" Width CNTR0 Input "L" Width Standard Min. 300 120 120 Max. - - - Unit ns ns ns Table 5.24 Symbol tc(TCIN) tWH(TCIN) tWL(TCIN) TCIN Input, INT3 Input Parameter TCIN Input Cycle Time TCIN Input "H" Width TCIN Input "L" Width Standard Min. 1,200(1) 600(2) 600(2) Max. - - - Unit ns ns ns NOTES: 1. When using the Timer C input capture mode, adjust the cycle time (1/ Timer C count source frequency x 3) or above. 2. When using the Timer C input capture mode, adjust the width (1/ Timer C count source frequency x 1.5) or above. Table 5.25 Symbol tc(CK) tW(CKH) tW(CKL) td(C-Q) th(C-Q) tsu(D-C) th(C-D) Serial Interface Parameter CLKi Input Cycle Time CLKi Input "H" Width CLKi Input "L" Width TXDi Output Delay Time TXDi Hold Time RXDi Input Setup Time RCDi Input Hold Time Standard Min. 300 150 150 - 0 70 90 Max. - - - 80 - - - Unit ns ns ns ns ns ns ns Table 5.26 Symbol tW(INH) tW(INL) External Interrupt INT0 Input Parameter INT0 Input "H" Width INT0 Input "L" Width Standard Min. 380(1) 380(2) Max. - - Unit ns ns NOTES: 1. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input HIGH width to the greater value, either (1/ digital filter clock frequency x 3) or the minimum value of standard. 2. When selecting the digital filter by the INT0 input filter select bit, use the INT0 input LOW width to the greater value, either (1/ digital filter clock frequency x 3) or the minimum value of standard. Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 33 of 35 R8C/16 Group, R8C/17 Group 5. Electrical Characteristics VCC = 3V tc(CNTR0) tWH(CNTR0) CNTR0 Input tWL(CNTR0) tc(TCIN) tWH(TCIN) TCIN Input tWL(TCIN) tc(XIN) tWH(XIN) XIN Input tWL(XIN) tc(CK) tW(CKH) CLKi tW(CKL) th(C-Q) TxDi td(C-Q) RxDi tW(INL) INTi Input tW(INH) tsu(D-C) th(C-D) Figure 5.6 Timing Diagram When VCC = 3V Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 34 of 35 R8C/16 Group, R8C/17 Group Package Dimensions Package Dimensions JEITA Package Code P-LSSOP20-4.4x6.5-0.65 RENESAS Code PLSP0020JB-A Previous Code 20P2F-A MASS[Typ.] 0.1g 20 11 HE *1 E F NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 1 Index mark 10 c A2 A1 *2 D Reference Symbol Dimension in Millimeters Min 6.4 4.3 Nom 6.5 4.4 1.15 1.45 0 0.17 0.13 0 0.1 0.22 0.15 0.2 0.32 0.2 10 6.4 0.65 6.6 0.77 0.10 0.3 0.5 0.7 Max 6.6 4.5 D E L A A2 A e y *3 bp Detail F A1 bp c HE e y L 6.2 0.53 Rev.2.00 Jan 30, 2006 REJ03B0101-0200 Page 35 of 35 REVISION HISTORY REVISION HISTORY Rev. 0.10 1.00 Date Sep 06, 2004 Feb 25, 2005 R8C/16 Group, R8C/17 Group Datasheet R8C/16 Group, R8C/17 Group Datasheet Description Page - 2-3 5 6 7-8 16 Summary 1.10 2.00 First Edition issued Tables 1.1 and 1.2 revised Table 1.3 and figure 1.2 revised Table 1.4 and figure 1.3 revised Figures 1.4 and 1.5 revised Table 4.1 revised: - 000Fh: 000XXXXXb 00011111b - 0036h: 00001000b 0000X000b and 01001001b 0100X001b 18 Tabel 4.3 revised: - 009Ch: FFh 00h; NOTES2 added - 009Dh: FFh 00h 21 Table 5.3 revised 22 Tables 5.4 and 5.5 revised 24 Tables 5.8 and 5.9 revised 25 Table 5.11 revised 26 Table 5.12 and figure 5.4 added 27 Table 5.13 revised 28 Table 5.14 revised 29, 33 Table 5.16 and 5.23 revised: Table title "INT2" "INT1" 31 Table 5.20 revised; NOTE revised 32 Table 5.21 revised 35 Package Dimensions revised May 26, 2005 5, 6 Tables 1.3 and 1.4 revised 16 Table 4.1 revised: - 0009h: XXXXXX00b 00h - 000Ah: 00XXX000b 00h - 001Eh: XXXXX000b 00h 22 Table 5.5 revised; NOTE revised 26 Fig 5.4 revised 27 Table 5.13 revised 31 Table 5.20 revised Jan 30, 2006 1 1. Overview; "20-pin plastic molded LSSOP or SDIP" "20-pin plastic molded LSSOP" revised 2 Table 1.1 Performance Outline of the R8C/16 Group; Package: "20-pin plastic molded SDIP" deleted 3 Table 1.2 Performance Outline of the R8C/17 Group; Package: "20-pin plastic molded SDIP" deleted, Flash Memory: (Data area) (Data flash) (Program area) (Program ROM) revised 4 Figure 1.1 Block Diagram; "Peripheral Function" added, "System Clock Generation" "System Clock Generator" revised 5, 6 Table 1.3 Product Information of R8C/16 Group, Table 1.4 Product Information of R8C/17 Group; revised. Figure 1.2 Part Number, Memory Size and Package of R8C/16 Group, Figure 1.3 Part Number, Memory Size and Package of R8C/17 Group; Package type: "DD : PRDP0020BA-A" deleted A-1 REVISION HISTORY R8C/16 Group, R8C/17 Group Datasheet Description Rev. 2.00 Date Jan 30, 2006 Page Summary 8 Figure 1.5 PRDP0020BA-A Package Pin Assignment (top view) deleted Table 1.5 Pin Description; Timer C: "CMP0_0 to CMP0_3, CMP1_0 to CMP1_3" "CMP0_0 to CMP0_2, CMP1_0 to CMP1_2" revised 10 Figure 2.1 CPU Register; "Reserved Area" "Reserved Bit" revised 12 2.8.10 Reserved Area; "Reserved Area" "Reserved Bit" revised 13 Figure 3.1 Memory Map of R8C/16 Group revised 14 3.2 R8C/17 Group; (program area) (program ROM), (data area) (data flash) revised Figure 3.2 Memory Map of R8C/17 Group revised Table 4.3 SFR Information(3); 0085h: "Prescaler Z" "Prescaler Z Register" 0086h: "Timer Z Secondary" "Timer Z Secondary Register" 0087h: "Timer Z Primary" "Timer Z Primary Register" 008Ch: "Prescaler X" "Prescaler X Register" 008Dh: "Timer X" "Timer X Register" 0090h, 0091h: "Timer C" "Timer C Register" revised Table 5.4 Flash Memory (Program ROM) Electrical Characteristics; * NOTES 1 to 7 added * "Topr" "Ambient temperature", "(Program area)" "(Program ROM)" revised Table 5.5 Flash Memory (Data flash Block A, Block B) Electrical Characteristics; * NOTE1 revised, NOTE9 added * "Topr" "Ambient temperature", "(Program area)" "(Program ROM)" revised Figure 5.2 Time delay from Suspend Request until Erase Suspend revised Table 5.7 Voltage Detection 2 Circuit Electrical Characteristics; NOTE1 revised Table 5.8 Reset Circuit Electrical Characteristics (When Using Voltage Monitor 1 Reset ); NOTE2 revised Table 5.9 Reset Circuit Electrical Characteristics (When Not Using Voltage Monitor 1 Reset); NOTE1 revised Table 5.10 High-speed On-Chip Oscillator Circuit Electrical Characteristics revised Table 5.12 Timing Requirements of I2C bus Interface (IIC); NOTE1 revised Table 5.14 Electrical Characteristics (2) [Vcc = 5V] revised "Timing Requirements (Unless ... at Ta = 25C) [ VCC = 5V ]" "Timing Requirements (Unless ... at Topr = 25C) [ VCC = 5V ]" revised Table 5.18 Serial Interface; "35" "50", "80" "50" Table 5.21 Electrical Characteristics (4) [Vcc = 3V] revised "Timing requirements (Unless ... at Ta = 25C) [VCC = 3V]" "Timing requirements (Unless ... at Topr = 25C) [VCC = 3V]" revised Table 5.25 Serial Interface; "55" "70", "160" "70" Package Dimensions; Package "PRDP0020BA-A" deleted 17 21 22 23 24 25 26 28 29 32 33 35 A-2 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. 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